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[VHDL-FPGA-Verilog] Verilog_FPGA_fp

Description: 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
Platform: | Size: 124928 | Author: xiong | Hits:

[MPI] arban

Description: 这是一个用verilog实现的除法器代码。-This is a realization of the use verilog divider code.
Platform: | Size: 1024 | Author: arban | Hits:

[VHDL-FPGA-Verilog] divider

Description: 介绍了除法器的设计，采用verilogHDL语言，利用modelsim仿真验证，压缩包中包含了流程图-Introduced the divider design, using verilogHDL language, the use of ModelSim simulation, compressed package that contains a flow chart
Platform: | Size: 83968 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] div2

Description: 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
Platform: | Size: 3072 | Author: 刘蒲霞 | Hits:

[VHDL-FPGA-Verilog] Frequency_divider

Description: 用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
Platform: | Size: 134144 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] 32divider

Description: 32位元2進位除法器 -32-bit binary divider 2
Platform: | Size: 2048 | Author: chen | Hits:

[VHDL-FPGA-Verilog] div

Description: 除法器实验 verilog CPLD EPM1270 源代码-Experimental divider verilog CPLDEPM1270 source code
Platform: | Size: 117760 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 基于Verilog的除法器设计，可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
Platform: | Size: 1024 | Author: 谢玮霖 | Hits:

[VHDL-FPGA-Verilog] devider

Description: a divider design based on verilog language
Platform: | Size: 2048 | Author: Xiao Yang | Hits:

[VHDL-FPGA-Verilog] dividers

Description: verilog格式的除法器，试过了，很好用，再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
Platform: | Size: 10240 | Author: miss zhang | Hits:

[ELanguage] 32bit

Description: multiplier and divider verilog codes
Platform: | Size: 6144 | Author: damasqas | Hits:

[VHDL-FPGA-Verilog] divide

Description: It is n-bit sequential divider in verilog language
Platform: | Size: 1024 | Author: Lisha | Hits:

[source in ebook] ref

Description: non-storing divider in verilog code
Platform: | Size: 1024 | Author: leo | Hits:

[VHDL-FPGA-Verilog] verilogfenpinqi

Description: verilog分频器代码 分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
Platform: | Size: 2048 | Author: 王楚宏 | Hits:

[VHDL-FPGA-Verilog] clock

Description: verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
Platform: | Size: 672768 | Author: luoxs | Hits:

[VHDL-FPGA-Verilog] clk_divider

Description: Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
Platform: | Size: 1024 | Author: h_j_tel | Hits:

[VHDL-FPGA-Verilog] divider

Description: verilog divider hardware
Platform: | Size: 29696 | Author: dumbmage | Hits:

[VHDL-FPGA-Verilog] dividerverilogdesign

Description: verilog 分频器设计 偶数分频器和奇数分频器-divider verilog design even and odd divider divider
Platform: | Size: 10240 | Author: lulu | Hits:

[VHDL-FPGA-Verilog] divider16

Description: 16位小数除法器verilog源码，可综合的，已经仿真过。-16bit fractional numeral divider verilog source
Platform: | Size: 1024 | Author: maxwellqq | Hits:
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